1. Field of the Invention
This invention relates to a high performance domino STATIC RANDOM ACCESS MEMORY (SRAM) in which the core memory cells are organized into sub-arrays accessed by local bit lines connected to global bit lines, and more particularly to an improved domino SRAM.
2. Description of Background
A static semiconductor memory typically includes six-transistor cell in which four transistors are configured as a cross-coupled latch for storing data. The remaining two transistors are used to obtain access to the memory cell. During a read access, differential data stored in the memory cell is transferred to the attached bit line pair. A sense amplifier senses the differential voltage that develops across the bit line pair. During a write access, data is written into the memory cell through the differential bit line pair. Typically, one side of the bit line pair is driven to a logic low level potential and the other side is driven to a high voltage level. The cells are arranged in an array that has a grid formed of bit lines and word lines, with the memory cells disposed at intersections of the bit lines and the word lines. The bit lines and the word lines are selectively asserted or negated to enable at least one cell to be read or written to.
As will be appreciated by those skilled in the art, in prior art domino SRAM design the cells are arranged into groups of cells, typically on the order of eight to sixteen cells per group. Each cell in a group is connected to a local bit line pair. The local bit line pair for each group of cells is coupled to a global bit line pair. Rather than use sense amplifier to detect a differential voltage when reading a cell, in a domino SRAM the local bit lines are precharged and discharged by the cell in a read operation, which discharge is detected and determines the state of the cell. The local bit line, the precharge means, and the detection means define a dynamic node of the domino SRAM. Domino SRAMs of the type discussed here are explained in greater detail in U.S. Pat. Nos. 5,729,501, 6,058,065 and 6,657,886, which are incorporated herein by reference.
In a domino SRAM array, in the read operation the cell must produce a bit line voltage large enough to drive off the SRAM macro with no help from a sense amplifier. In this situation, the “write” operation becomes the primary design focus due to a situation called “Fast Read before Write”.
The problem occurs when a cell is slow to write but very fast to read, which can result in both of the local bit lines being pulled down to ground making the cell un-writable. For example, during a write to the opposite state, the “write transistor” in the “local bit selector” pulls down on one “local bit line”, while the cell pulls down on the opposite “local bit line”, resulting in both “local bit lines” being pulled down to ground, thereby preventing the cell from writing. A cell that is slow to write, but very fast to read, is caused by manufacturing process variations. Due to device parametric variations, the PFET could be skewed to the strong side and the NFET to the weak side, making the NFET pass gate more difficult to overcome the PFET in a write operation. If the device and metal capacitance is on the low side, and the NFET pass gate threshold voltage Vt is low, the cell could have a fast read.
A similar problem can occur when a timing mismatch takes place between the “row” select and the “column” select lines. For example, if the row line becomes active before the write signal arrives at the “local bit select”, the cell is in read mode before the write can occur, resulting in a similar situation where both “local bit lines” are pulled down to ground leaving the cell in a “un-writeable” state. (Remember, 6T cells are good at pulling down on their local bit lines, but poor at pulling up because their pass gates are NFETs.) This “Fast Read before Write” is not a problem in traditional SRAM designs using sense amp's because the “bit selector” used there has bit line clamps to prevent this from occurring. Also, the traditional approach has more cells on a bit line (i.e. on the order of 128-to-256 cells vs. 8-to-16 cell in our new approach) making the bit lines much more capacitive and much slower to develop a voltage differential; therefore, making it less likely to have the “Fast Read before Write” situation even without the clamps. One way to minimize the problem in Domino Read SRAMs is to “push-out” the “row” select signal to guarantee the “write data” is available to the local bit line before the cell is selected. However, some cells will still cause a “Fast Read before Write” because they are “slow to write but very fast to read” even though they are within the normal manufacturing window. This solution results in a performance slow-down and does not solve or prevent the un-writeable state.